Two-Dimensional Device Simulation for Polycrystalline Silicon Thin-Film Transistor

An accurate device simulator for polycrystalline silicon thin-film transistors is developed. In this simulator, the influences of grain boundaries (GBs) are incorporated into the mobility model, and the basic semiconductor equations are solved combining with the carrier generation/recombination model. As a result, it becomes possible to quantitatively analyze the influence of the GBs on the kink effect and the avalanche breakdown phenomenon, and the influences of the GB trap density and the grain size on the device characteristics.