Wafer Scale Solution Processing of 2D Transistors and Circuits With High Mobility Single‐Flake Transport

Solution‐processed 2D semiconductor‐based thin film transistors (TFTs) offer a pathway to achieve flexible and large‐area electronics. However, their performance is typically limited by the inter‐flake resistance that masks the intrinsic electronic properties of these materials. This is because conventional hydrodynamics‐driven solution deposition techniques lack precise flake placement ability, and result in a stochastic multi‐flake network, leading to low device mobility and large variability. Here, we demonstrate that dielectrophoretic assembly can precisely align 2D MoS 2 flakes from an ultra‐low‐concentration dispersion (1.2 µg mL −1 ) into predefined channel regions, resulting in high mobility single‐flake transport. This approach enables assembly of 16,000 devices on a 3‐inch wafer with >97% yield. With printed electrolyte gating, these fully solution‐processed TFTs show an average On/Off ratio > 10 6 and device mobility of 51 cm 2 V −1 s −1 . Further, they demonstrate excellent stability under switching operations, electrical bias‐stress, and dynamic mechanical tests. When compared with the multi‐flake devices, the single‐flake architecture delivers more than a fourfold increase in device mobility. The concept has also been validated by fabricating functional logic gates and circuits. This generic approach to fabricate large‐area, single‐flake TFTs with low variability establishes a pathway for high‐performance, scalable solution‐processed 2D electronics.