Lightweight AI for constrained edge IoT systems via digital twin-driven optimization: A systematic literature review with taxonomy, benchmark contextualization, and critical gap analysis

Resource-constrained devices — including low-power Internet of Things (IoT) nodes, microcontrollers, and edge computing platforms — have positioned on-device intelligence as a critical enabler for next-generation cyber–physical systems. Although prior surveys have addressed lightweight AI techniques and Digital Twin (DT) technology in isolation, no existing systematic review concurrently examines their co-optimization for microcontroller-class edge deployment, critically evaluates simulation fidelity gaps, or quantifies the security void in integrated DT-AI frameworks . This Systematic Literature Review (SLR) fills that gap. Following the Kitchenham and Charters methodology augmented with PRISMA 2020 reporting, we screened 247 initially retrieved records down to 97 after applying inclusion/exclusion criteria, and systematically analyze the resulting 59 eligible peer-reviewed studies (2015–2025) sourced from five major digital libraries — ACM Digital Library, IEEE Xplore, ScienceDirect, Scopus, and MDPI — of which 47 met a stricter quality-assessment threshold used for a robustness check (Section 3.5). Our contributions go beyond prior descriptive surveys in five critical respects: (i) a four-dimensional taxonomy classifying each study by lightweight AI technique, DT functional role, target hardware platform, and evaluation scope — revealing that the dominant study profile (INT8 post-training quantization, no Digital Twin, simulation proxy, single efficiency metric) leaves the most constrained IoT hardware largely uncharacterized; (ii) a quantitative simulation-fidelity analysis showing that DT-based energy and latency estimates exhibit up to 60% error on real microcontroller hardware, a limitation systematically ignored in prior work; (iii) a critical finding that only 5 of 59 studies (8.5%) use Digital Twins as active optimization drivers rather than passive monitors — exposing a structural gap between claimed and realized DT potential; (iv) a security audit showing that no reviewed study integrates security scoring into model selection or uses a DT environment for adversarial testing; and (v) the explicit finding that only 8 of 59 studies (13.6%) validate on microcontroller-class hardware at all, meaning most reported efficiency gains in the reviewed literature remain unverified on the very device class that motivates the field. Benchmark contextualization against MLPerf Tiny reference values and cross-study UCI HAR results is provided to ground identified gaps in quantitative evidence. Seven prioritized research gaps and a corresponding forward-looking research agenda are proposed, focusing on MCU-validated DT-driven co-optimization pipelines and security-aware model selection.