High dI/dt Pulse Switching of 1.0 cm2 SiC GTOs

The Army Research Laboratory has collaborated with Cree, Inc. and Silicon Power Corp. to develop 9 kV-blocking, 1.0 cm2 Super-GTOs. In this study, several 1.0 cm2 GTOs were individually switched up to 6.0 kA in a low-inductance, high dI/dt (2.1 kA/µs) circuit to evaluate turn-on delay and optimize the gate control. Turn-on delay was evaluated relative to gate drive current, and the delay was reduced by 1.1 µs when gate amplitude was increased from 1 A to 8 A. Increasing gate current delivered to each GTO also successfully reduced variation in turn-on delay from device to device by at least 50%, and mitigated mismatch in turn-on between pairs of GTOs switched in parallel. As silicon carbide material processing and device development continue to evolve, the ultimate solution will be to reduce remaining material defects and to control minority carrier diffusion length through more uniform doping across the wafer. These steps will enable modules of parallel GTOs to perform at maximum capability.