Hybrid integration of advanced CMOS electronics and a high-performing silicon photonics platform, combined with wafer-scale testing and assembly processes have enabled delivery of low-cost, low-power, high-performance, high-volume optical transceivers. In this paper, we will discuss the aspects of each of these factors that have been critical in achieving this success. In particular, we will focus on the silicon photonics process, device library and design kit, the innovative solutions for wafer-level testing and assembly of the optical transceivers, and discuss the benefits and drawbacks of monolithic and hybrid electronics-photonics integration and the impact on the roadmap of future optical transceivers.
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Pinguet et al. (2018) studied this question.
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