Spur Analysis and Linearity Enhancement in Fractional-N Phase Locked Loops Through Parallel Sigma–Delta Modulators With Time Offsets

This article presents a theoretical framework for deriving simple analytical expressions for spurs resulting from second and third order nonlinearities in fractional-N phase locked loops (PLL). Furthermore, a previously proposed linearization technique where several sigma-delta modulators (SDMs) operate in parallel with relative time offsets between them, is further analyzed using the periodic nonlinearity noise (PNN) framework. Closed form expressions are derived for the spur components associated with second and third order nonlinearities, as well as for the expected suppression achieved by the linearization technique depending on the number of SDMs used. In particular, the effect of the accompanying phase rotation introduced by time-offsetting the SDMs is investigated under two conditions: one in which the phase rotation is compensated, and another in which it is left uncompensated. The analysis shows that effective suppression of third order nonlinearities requires compensating for this phase rotation. However, the suppression of second order nonlinearities remains largely insensitive to phase alignment, demonstrating robustness of the technique to phase offsets in that case. In addition, the quantization-noise interaction between the different parallel SDM paths is examined and characterized through simulations. The results demonstrate that the technique significantly improves linearity while also suppressing quantization noise from the SDM. Finally, an efficient hardware implementation is proposed.