A high speed 1:4 demultiplexer IC architecture featuring output bit alignment, reduced gate count, and improved timing over a conventional tree-type architecture demultiplexer is presented. Simulation results at 20 Gbit/s are obtained using an HBT process. The architecture can be directly extended to higher order demultiplexers, and is applicable to other processes supporting current-mode logic.
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Klaus R. Runge (1991) studied this question.