Numerical investigation of hybrid taper–grating coupling for broadband fiber-to-chip interfaces in silicon photonics

One of the most critical bottlenecks in photonic integrated circuit packaging in today’s scenario is efficient optical coupling between single-mode fibers (SMFs) and silicon-on-insulator (SOI) photonic chips. This is due to the severe mode-field diameter mismatch, which exceeds 20:1. This paper presents a simulation-based analysis of four fiber-to-chip coupling architectures on the 220 nm SOI platform: butt coupling, grating coupling, adiabatic taper coupling, and a proposed hybrid taper–grating design. All results are derived from full electromagnetic simulation using Lumerical FDTD Solutions v8.25 and RSoft BeamPROP 2023, without physical fabrication. The hybrid structure combines a 100 µm exponentially graded inverse taper with a 20-period apodized surface grating, optimized using a particle-swarm algorithm (40 particles, 150 iterations). Simulation predicts 97 % coupling efficiency, 0.35 dB insertion loss, 160 nm 3 dB bandwidth, and ±2.5 µm lateral misalignment tolerance improvements of approximately 35 % in efficiency and 100 nm in bandwidth relative to the standalone grating coupler baseline. Fabrication tolerance analysis over ±55 nm dimensional variation confirms predicted insertion loss penalties below 0.5 dB. Physical fabrication and experimental validation on the imec iSiPP50G platform are planned as the immediate next step.