Low‐Crosstalk Silicon Photonic Switch Fabrics for AI Datacenters and High‐Capacity Optical Interconnects: Device‐Level Origins and Mitigation

Silicon photonic switch fabrics are increasingly attractive for AI datacenters and high‐capacity optical interconnects, where optical circuit switching is being explored to support bandwidth‐intensive and dynamically reconfigurable connectivity. However, scaling silicon photonic switches to large port counts is fundamentally constrained by accumulated crosstalk, insertion loss, and device‐level non‐idealities. Suppressing crosstalk through additional architectural complexity can, in turn, compromise integration density and scalability. This article establishes a device‐to‐link‐to‐system framework for analysing the origins, accumulation, and mitigation of crosstalk in silicon photonic switch fabrics. Representative MZI, MRR, and RAMZI switching elements are examined to clarify how coupler imbalance, critical‐coupling deviation, and resonance‐induced amplitude–phase coupling impose extinction‐ratio limits and accumulate in large‐scale fabrics. Mitigation strategies are organised across device, circuit, and control levels to highlight their trade‐offs in crosstalk suppression, scalability, and implementation complexity. As a device‐level example, a tunable curved directional coupler is experimentally demonstrated as a compact primitive for post‐fabrication coupling‐ratio correction. Integrated into a 4 × 4 double‐layer‐network switch, it enables all 16 routing paths to exhibit crosstalk below −40 dB over a 10 nm bandwidth. All‐path 1.6 Tb/s IM/DD transmission experiments and link‐level simulations further connect device‐level crosstalk suppression to high‐capacity short‐reach operation and symbol‐rate‐dependent crosstalk tolerance.