Morphotropic Phase Boundary Engineering in HfO2-Based High-k Dielectric Nanosystems for Dynamic Random-Access Memory Capacitors: A Review

HfO2-based dielectrics engineered into an MPB-like regime have emerged as promising candidates for next-generation dynamic random-access memory (DRAM) capacitors because they offer enhanced dielectric permittivity while preserving the wide bandgap and CMOS compatibility of fluorite-structured oxides. At the nanometer-scale film thicknesses and grain dimensions relevant to DRAM, surface and interface energies, electrode confinement, stress, and defect distributions strongly reshape the relative stability and accessibility of fluorite-derived phases. However, the physical origin of the high-k response and its relationship with leakage current and reliability remain under active discussion. In this review, we summarize recent progress in HfO2-based MPB dielectrics from three perspectives. First, we discuss two complementary interpretations of dielectric enhancement: spatial phase coexistence between orthorhombic and tetragonal phases at the MPB, and dynamic nonlinear dielectric response associated with low transition barriers and field-induced structural evolution. Second, we review major engineering strategies for achieving MPB-like behavior, including stoichiometric and oxygen-vacancy control, advanced annealing processes, doping, bilayer and superlattice heterostructures, and electrode/interface engineering. Third, we evaluate the practical performance and reliability requirements for DRAM applications, with emphasis on the coupled trade-offs among dielectric constant, leakage current, equivalent oxide thickness, and time-dependent dielectric breakdown. Representative reports include k ≈ 67 with a leakage current density of 3 × 10−8 A/cm2 at 0.8 V and, in a separate ultrathin HZO device, an EOT of approximately 2.42 Å with k ≈ 64.24. Finally, we highlight that the optimization of MPB HfO2-based dielectrics requires a holistic design framework that simultaneously considers phase stability, defect dynamics, interface quality, and realistic low-voltage benchmarking conditions.