A configurable high-resolution SoC-based Time-to-Digital Converter in Artix-7 FPGA

This work presents the design and implementation of a high-resolution Time-to-Digital Converter (TDC) integrated within a System-on-Chip (SoC) architecture in an AMD Artix-7 FPGA. The system is built around a MicroBlaze processor operating at 100 MHz, with the Advanced eXtensible Interface (AXI) serving as a memory-mapped interconnect between the processor and peripheral modules. A high-resolution TDC core with an AXI interface is developed and seamlessly integrated into the MicroBlaze-based system. The TDC employs a flash-based architecture comprising coarse and fine time measurement stages. The coarse time is obtained using a counter operating at 200 MHz (5 ns resolution), while fine time interpolation within a clock period is achieved using a delay-line-based approach. Multiple TDC configurations with programmable time resolutions of 62.5 ps, 31.6 ps, and 16.1 ps are implemented. The system achieves a wide dynamic range exceeding 2 s while maintaining high timing precision. The measured single-shot timing resolutions are better than 41 ps, 33 ps, and 24.1 ps for the respective configurations.