Single event transient effects and variability in hybrid RRAM-CMOS spiking neural network

The spiking neural network (SNN) uses discrete spikes exploiting parallel, event-driven computations to process large amount of digital data, replicating the behavior of human brain. The SNN circuit has a leaky-integrate and fire (LIF) neuron and resistive RAM (RRAM) synaptic array with in-situ weight update through spike timing-dependent plasticity (STDP) mechanism. The single event transients (SET) due to particle strikes are major reliability threat for high speed integrated circuits. The effect of single event transients (SET) in 1T-1R RRAM synaptic array and CMOS LIF neuron circuit are analyzed in this paper. The SET due to single and multiple strikes create additional spikes and timing variations in the output spikes and affect the pattern/digit recognition. The RRAM synapses in SNN are implemented using Stanford RRAM model and the effect of parameter variations in the discrete output spikes are analyzed. The mitigation techniques to suppress the SET and model parameter variations in SNN circuit are proposed.