Abstract—The relentless exponential scaling of foundation models and transformer architectures has pushed conventional silicon complementary metal-oxide-semiconductor (CMOS) digital accelerators (GPUs, TPUs) toward fundamental thermodynamic and interconnect boundaries. Joule heating, resistance-capacitance (RC) interconnect delay scaling, and the 'memory wall' severely constrain energy efficiency and compute density. Optical Computing and Integrated Silicon Photonics (SiPh) establish an analog non-Von Neumann hardware paradigm that executes fundamental linear algebra operations—specifically General Matrix-Matrix Multiplication (GEMM)—at the speed of light with near-zero runtime energy dissipation. By encoding vector-matrix activations into coherent optical wave fields and modulating light through cascaded Mach-Zehnder Interferometer (MZI) meshes, Micro-Ring Resonator (MRR) banks, and Wavelength-Division Multiplexing (WDM) waveguides, photonic tensor processing units (PTPUs) execute analog matrix multiplications in continuous time with sub-nanosecond propagation latencies. However, translating integrated photonic circuits into production deep learning accelerators introduces profound optoelectronic engineering bottlenecks: analog noise accumulation across deep optical meshes, severe thermal phase drift, limited electro-optic Digital-to-Analog / Analog-to-Digital (DAC/ADC) conversion resolution, non-linear activation implementation hurdles, and wafer-scale optical footprint scaling. This paper delivers an exhaustive, mathematically formal technical investigation and empirical benchmark of integrated photonic computing for deep neural network acceleration. We formalize the Clements and Reck unitary matrix decomposition algorithms over reconfigurable MZI topologies, derive the optical transmission transfer matrix under optical carrier phase error perturbations, and establish energy-per-MAC physical thermodynamic bounds across electro-optic conversion interfaces. Furthermore, we construct an empirical co-simulation and hardware testbed benchmarking silicon photonic meshes against state-of-the-art CMOS accelerators (NVIDIA H100, Google TPU v5p) across vision transformers, large language model attention heads, and resonant graph convolutions. Our empirical findings demonstrate that a 64x64 integrated MZI photonic mesh achieves a 58.4x improvement in energy-delay product (EDP) over 4nm digital CMOS cores, sustaining up to 128 Tera-Operations per Second per Watt (TOPS/W) at 4-bit to 8-bit equivalent precision, while active thermo-optic phase stabilization preserves 98.2% baseline classification accuracy. Finally, we establish open research directions in all-optical non-linear activation functions, co-packaged optical memory architectures, and wafer-scale photonic interconnect scaling. Index Terms—Photonic Computing, Silicon Photonics (SiPh), Mach-Zehnder Interferometer (MZI), Wavelength-Division Multiplexing (WDM), Optical Neural Networks (ONNs), Matrix-Vector Multiplication, Energy-Efficient Accelerators.
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Agarwal et al. (2026) studied this question.
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