Parallel accelerated steganographic polar coding architecture based on GPU

High-throughput steganographic coding remains difficult because syndrome-trellis codes (STC) incur high computational cost at practical security settings, while steganographic polar codes retain strong serial dependencies in their successive decoding schedule. This paper proposes CuSPC, a GPU-oriented steganographic polar coding architecture that restructures simplified successive cancellation (SSC) execution, introduces an ordinary-node (Ord) design for short residual subtrees, and combines inter-cover parallelism with interleaved global-memory access. The implementation maps intra-node, inter-node, and inter-cover parallelism to the CUDA execution model while preserving the distortion-minimizing formulation of polar steganographic coding. Experiments show that CuSPC reaches up to approximately 39 Mb/s across the tested devices and improves throughput by about 30 times over the CPU serial baseline, while keeping the coding loss below 2% and maintaining steganalysis performance comparable to mainstream baselines.