An Energy Efficient Multi-Retention STT-MRAM Memory Architecture for IoT Applications

This brief proposes a novel energy-optimized multi-retention STT-MRAM architecture for IoT devices that addresses the limitations of the traditional memory architecture consisting of flash and SRAM. We first extensively investigate the IoT applications behavior and their memory access pattern to classify the memory addresses based on their lifetime. Then, we determine optimum points of STT-MRAM retention relaxation for energy saving and propose a memory allocation scheme to map the application blocks in their most energy efficient memory section. Our evaluations demonstrate that the average energy saving of the proposed architecture is 66% compared to the conventional STT-MRAM architecture.