Through-silicon via (TSV) structures act as vertical interconnections for 3D packaging in defense and aerospace precision devices, making their mechanical performance evaluation critical. This paper aims to reveal the influence of grain boundaries (GBs) on the mechanical properties of TSV-Cu. Micron-scale crystal plastic parameters of TSV-Cu were calibrated via nanoindentation experiments, and constitutive simulations incorporating dislocation density evolution matched well with experimental results. Experimental phenomena of three grain orientations, namely [001], [011] and [111], further verify the validity of nanoindentation simulations. Based on stored energy density ( G ba ) criteria and for GB effects, grain misorientation within 5°∼30° showed negligible property variations, while high angle grain boundarie (HAGBs, θ = 45°) degraded TSV-Cu mechanical properties by 17.4% and maximized G ba distribution, implying high crack initiation risk, consistent with experimental observations at θ = 45.77°. CPFE-based fatigue analysis of the polycrystalline representative volume element (RVE) finite element model shows that crack initiation sites are mainly located at GBs between adjacent grains with high Schmid factor μ values. The observed grain boundary misorientation θ ranges from approximately 43.96° to 48.45°, which is consistent with the indications from nanoindentation simulations and actual fatigue test results. Furthermore, HAGBs with θ of 45° ± 3.45° are defined as the microstructural weak regions of TSV-Cu with a high probability of inducing crack initiation. In contrast, TBs exert a positive effect on the strength improvement of TSV-Cu.
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Li et al. (2026) studied this question.
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