A New Approach to Analysis and Synthesis of Incompletely Defined Sequential Systems

The Present paper refers to an interesting topic regarding the analysis and synthesis of incompletely defined digital sequential systems. For these systems, the number of states is different from 2k, where ‘k’ represents the bits of the state code, and the difference is represented by the so-called parasitic states, as the states where the system may be accidentally. For cost reasons, systems are usually designed with a small number of states, which is why the system could transit a parasitic state, and we can say that the system presents a digital logic hazard. The digital logic hazard can be induced into the system due to electromagnetic interference, parasitic signals due to voltage inputs, defects of the circuits, system hazards, etc. The novelty of the digital system synthesis solution proposed in this paper consists of taking into account the transitions for parasitic states to the initial reset state.