Methods for organising the data storage and transmission subsystem in a hardware accelerator for convolutional neural networks

Modern Edge AI systems use specialized hardware neural network accelerators to process large amounts of data directly on user devices. The main challenges in organizing the data storage and transfer subsystem in hardware accelerators are limited bus bandwidth, limited memory capacity, and high requirements for processing speed and energy consumption. The growing demands on the performance and energy efficiency of neural network processors in the context of limited resources in embedded systems make it relevant to study the methods of organizing the data storage and transfer subsystem. The article proposes options for the architectural organization of the data storage and transfer subsystem: with full control from the central processor, with caching in BRAM-type memory, with direct access to memory through the common AXI_GP bus, and with a dedicated high-speed AXI_HP bus. To evaluate the efficiency, the article uses the method of simulating the inference of the convolutional layer of the YOLOv5s neural network on a neural network processor model at the register transfer level, calculating the bandwidth and performance for each option. As a result of the study of the dependence of the characteristics of the neural network processor on the method of organizing the data storage and transmission subsystem, it was found that the developed neural network processor achieves a maximum performance of 240 GOPS. The advantage of using a direct access interface to RAM with a bandwidth of 1.2 GB/s, which is dedicated for data transmission for calculations, has been confirmed. The comparison showed that the use of direct memory access with a dedicated high-speed interface can increase the performance of inference of neural networks by an average of 20 times. The described methods for organizing the data storage and transfer subsystem achieve a performance that is 1.19 times higher than that of analogues on convolutional neural network inference tasks. The results demonstrate the potential for using these methods in the design of hardware accelerators for Edge AI systems.