FPGA-Based Time-Triggered Ethernet with a Decoupled Control–Data Architecture and a Deadline-Aware Weighted Load-Balancing Traffic Scheduling Method

Time-Triggered Ethernet (TTE, SAE AS6802) ensures deterministic communication for safety-critical distributed systems, but hardware implementation requires tight coordination between clock synchronization and schedule execution. This paper presents an FPGA-based TTE interface featuring a decoupled control–data architecture and an offline deadline-aware weighted load-balancing method. The control plane implements hardware-level AS6802 synchronization functions, while the data plane executes schedule-triggered UDP frame transmissions using a common 125 MHz logical time base (8 ns resolution). To balance channel utilization while guaranteeing timeliness, Earliest Deadline First (EDF) instance ordering is combined with transmission-duration-weighted load balancing over candidate transmission positions. The system was validated on two Xilinx Artix-7 FPGAs interconnected via a direct 1 Gb/s link. Experimental results demonstrate that the PCF timestamp-interval residual remains within ±8.00 ns (mean absolute error of 2.88 ns), while the measured compensated physical clock skew between independent boards is 0.71 ± 3.58 ns with a maximum of 9.60 ns. For the evaluated five-flow TT workload (13 instances per 32 ms matrix cycle), the interface achieves a mean end-to-end hardware latency of 2.45 ms (maximum 3.78 ms), zero packet loss, zero deadline violations, and a 96.97% load-balance rate across the configured logical channels.