A 65-nm precision-reconfigurable neuromorphic digital compute-in-memory macro with aligned storage for synaptic weights and membrane potentials

Compute-in-Memory (CIM) provides an effective hardware approach for reducing data movement in Spiking Neural Network (SNN) inference. However, conventional digital CIM macros are mainly organized around static synaptic weights and do not efficiently support the recurrent read-update-write access of membrane potentials. The mismatch between low-bit-width weights and higher-bit dynamic membrane potentials can lead to array fragmentation, additional buffering, and inefficient local state updates. To address this challenge, this paper proposes a 65-nm 10T-SRAM-based digital CIM macro with aligned storage for synaptic weights and membrane potentials. Through an optimized storage architecture, the design not only maximizes storage utilization but also supports flexible synaptic weights (4/8/12-bit) and membrane potentials (8/16/24-bit) configuration. Further, this CIM macro supports single-cycle membrane potential accumulation, eliminating redundant intermediate result buffering. Simultaneously, sign arithmetic logic is embedded in the pre-charge circuit, and the accumulator is repurposed for threshold comparison and spike decision, maximizing computational efficiency at minimal hardware overhead. Post-layout simulations in a 65-nm CMOS process show that the macro achieves 0.616 pJ/SOP at 1.0 V and 100 MHz. Under the same macro-level SOP definition and sparsity assumption, the proposed design reduces membrane-potentialrelated storage overhead by at least 40% and shows more than 4× energy-efficiency improvement compared with representative digital SNN-CIM designs.