Dry-Process Engineering for Wafer-Scale Perovskite/Silicon Tandem Solar Cells: From Textured-Surface Conformality to M10 Manufacturing

Monolithic perovskite/silicon tandem solar cells have reached certified efficiencies above 35% at small area, while large-area devices have reached the mid-30% range and full-area M10 tandems have exceeded 28%. Translating these gains to industrially standardized textured silicon wafers introduce a different class of manufacturing constraints. Although dry processing removes solvent-wetting and drying-front instabilities, it does not intrinsically guarantee conformal, compositionally uniform, or defect-free coverage on realistic silicon textures. The central problem is no longer simply whether a wide-bandgap perovskite can be deposited from the vapor phase, but whether a complete top-cell stack can be formed reproducibly over M6-, M10-, and ultimately G12-class wafers while preserving local texture coverage, composition, interface integrity, cycle time, and yield. This focused review examines dry-process engineering for wafer-scale perovskite/silicon tandems, with emphasis on the textured-surface problem, multi-source and sequential evaporation, close-space sublimation, dry carrier-selective contacts, transparent-electrode integration, source geometry, process monitoring, materials utilization, maintenance, and in-line metrology. We distinguish true conformal coating from valley filling or partial planarization and argue that dry deposition should be judged at the stack and wafer levels rather than by absorber uniformity alone. Finally, we propose manufacturing-oriented qualification metrics and a staged roadmap from texture-robust deposition to M10/G12 repeated-batch yield and reliability.