An RV32IMC Processor with a Tightly Coupled Linear Classifier Accelerator for Edge AI Inference

Edge AI inference on resource-constrained devices demands low latency, minimal memory footprint, and tight power budgets---requirements that cloud-based inference cannot satisfy due to network latency, bandwidth, and privacy costs. This paper presents the design of an RV32IMC processor tightly coupled with a custom ISA-extended linear-classifier accelerator, described in synthesizable SystemVerilog RTL and evaluated through cycle-accurate simulation. The processor implements the RISC-V RV32I base integer set, the M extension for hardware multiply/divide, and a partial C extension for 16-bit compressed instructions. A 4×4 weight-stationary systolic array is integrated directly into the execute stage of a five-stage pipeline via four custom instructions encoded in the reserved custom-0 opcode space (0x0B). Cycle-accurate RTL simulation on Vivado xsim shows that the hardware accelerator completes a 4-class linear-classification inference in 19 cycles, a 4.2× speedup over an RV32IM software baseline (79 cycles) and a 40.1× speedup over a realistic RV32I general-purpose software baseline (761 cycles). The C extension delivers a 24.24% code-size reduction (528 B → 400 B) with zero performance penalty, via a purely combinational decompressor in the fetch stage. These results indicate that tightly coupled, domain-specific ISA extensions on a compact RISC-V core can deliver meaningful inference acceleration for edge deployment while preserving the modularity of the RISC-V ecosystem. FPGA synthesis and on-hardware characterization were not performed in this work and are identified as future work.