Single-Ended 7T SRAM Cell Design Using 18 nm FinFET Technology for Low-Power and High-Stability Nanoscale VLSI Applications

This study presents the design and performance evaluation of a single-ended seven-transistor (7T) static random-access memory (SRAM) cell in 18 nm fin field-effect transistor (FinFET) technology for low-power, high-stability nanoscale very-large-scale integration (VLSI) applications. The cell combines separate read and write bitline paths, a transmission-gate (TG) read port that removes read-bitline precharging and substantially reduces read disturb, and a virtual-ground (VGND) power-gating scheme that suppresses subthreshold leakage through the body effect. The cell is benchmarked against nine existing topologies (6T, 7T, two 8T, 9T, 10T, and three Schmitt-trigger cells), all re-simulated at the same 18 nm FinFET node to remove cross-technology bias. The evaluation covers hold, read, and write static noise margins (SNM), write-trip voltage, access time, dynamic and leakage power, and energy-delay product (EDP), together with five-corner process-voltage-temperature (PVT) analysis and Monte Carlo simulation with 1000 samples. The proposed cell reduces leakage power by 75.6% relative to a conventional 6T cell, achieves the highest write-trip voltage (615.2 mV) of all compared cells, and ranks fourth-lowest in normalized EDP, at an estimated area of 1.18 times that of the 6T cell. The combined Monte Carlo functional yield is 96.9% to 97.8%. The VGND-float write assist that maximizes the write-trip voltage also weakens the hold-mode pull-down strength, so the cell has the lowest static voltage noise margin of the compared topologies. All results are obtained from schematic-level (pre-layout) simulation. Within these limits, the cell is a suitable candidate for last-level cache and embedded memory in area- and power-constrained mobile system-on-chip applications.