Inverted MAML & Forward Hadamard Propagation (FHP): Physical Silicon Verification, Spatially Correlated LLM Benchmarks, and Multi-Layer Atomic Triads (SE 2630397-4)

This dataset and open-source hardware release presents the complete design, FPGA firmware, and physical silicon validation of Inverted MAML (Model-Agnostic Meta-Learning) Analog In-Memory Computing (AIMC) (Patent Application SE 2630397-4). The system implements an analog atomic triad matrix processor utilizing discrete Dual-2T1C differential analog triode multiplier cells for ultra-low-power, real-time matrix-vector multiplication with continuous closed-loop drift and temporal capacitor decay compensation. Key Innovations & Architecture Atomic Triad Analog Matrix Structure: Integrates primary payload compute (Matrix 33, 6×6), first-layer carrier modulation (Matrix 3, 8×6 with analog Sigmoid activation), and second-layer Vernier drift compensation (Matrix 8, 7×6) summing directly at the transimpedance amplifier (ColTIA) virtual ground. Forward Hadamard Gradient Extraction (Non-Backpropagation): Forward perturbation voltages (V_PTU) are orthogonally coupled via zero-DC Walsh-Hadamard sequences into 2T1C storage nodes while input vectors x are held stationary. Gradients are extracted in real time via Fast Walsh-Hadamard Transform (FWHT) directly from analog physics without digital backpropagation. Dual FPGA SoC Digital Control: Controlled by an Efinix Trion T120 BGA324 Master SoC (RISC-V Sapphire soft core, 100 Hz capacitor refresh engine, UDP telemetry streaming) coupled to an Efinix Trion T20 BGA256 Gate & Hadamard driver node. - **Milestone 1 & 2 Silicon Validation (Fixed 5.0 ms Operating Point):** - **Milestone 1 (In-Situ Gradient Extraction):** Validated on physical silicon that all partial derivatives can be extracted from an unknown analog neural network in single-shot O(1) time using Forward Hadamard Propagation (FHP) without backpropagation or mathematical transistor modeling. - **Milestone 2 (Dynamic Error Compensation):** Demonstrated on physical 2T1C silicon that active Inverted MAML elevates sustained resolution from a hardware ground floor of ~3.4 bits (43,003 LSB² loss) to ~4.0 bits ENOB (-59.6% quadratic loss) under continuous multivariate white noise across the entire input volume. - **Enhanced Performance on Correlated Vectors:** Spatially correlated autoregressive input vectors (LLM Toeplitz KMS AR(1), ρ = 0.85) yield even stronger compensation, elevating sustained precision to 5.79 bits mean ENOB with peaks reaching 7.13 bits. *(Milestone 3 active work-in-progress: Sweeping temporal discharge windows from 4.5 ms to 5.5+ ms to establish hardware decay bounds).* Package & Repository Contents Hardware CAD & EDA (v2.0): Complete EasyEDA Pro project files (.epro2), interactive schematics, Gerber fabrication files, Pick-and-Place (CPL), and verified Bill of Materials (BOM). FPGA Synthesis & Firmware: Verilog RTL synthesis projects for Efinix Trion T120 & T20, timing constraint files (.sdc), and RISC-V embedded C firmware with multi-strata batch update algorithms. Calibration & Telemetry Suite: Python real-time GUI, hardware UDP client, automated regression testers, and 500-epoch silicon telemetry datasets. Documentation & Engineering Reports: Detailed mathematical derivations of forward Hadamard gradient extraction, ColTIA saturation guard protocols, and PDF characterization reports. Open Science & Hardware Links GitHub Repository: https://github.com/ollewelin/analog_matrix_computation_Inverted_MAML_PAT_PEND_2630397-4 OSHWLab Project (Schematics & CAD): https://oshwlab.com/olle_welin/project_yvkekxrp YouTube Video Demonstrations: Architecture & Operating Principle: https://youtu.be/uo66-gnDks0 Physical Silicon Hardware Demo: https://youtu.be/F365JVFYOdE In-Depth System Walkthrough: https://www.youtube.com/watch?v=LbWriQ0J6QY&t=615s License & Patent Information This project is released under Creative Commons Attribution 4.0 International (CC BY 4.0) for documentation and datasets, with hardware designs under CERN-OHL-P v2 and firmware under Apache 2.0 / MIT. Associated patent application: SE 2630397-4 (Patent Pending, Open Science Hardware Release).