Experimental Feasibility-Driven Spacer Material Engineering for Improved Performance in Novel E-shaped Nanosheet FET at Sub-5 Nm Technology Node: Device to Circuit Level Insights

This work presents the first comprehensive investigation of spacer engineering in a novel E-shaped Gate-All-Around (GAA) nanosheet (NS) FET at sub-5 nm node, where the primary novelty lies in the introduction of the E-shaped channel geometry to enhance electrostatic control and effective channel width. Analysis of both single-κ and dual- κ spacers is provided for digital, analog/RF, and circuit designs. The single- κ spacers exhibit substantial benefits from higher κ value ranging from 1 to 39 in achieving better on-off current ratio ( I ON / I OFF ) and reduced subthreshold swing (∼9%), along with enhanced intrinsic gain (∼42%), even though it leads to three times higher gate capacitance and 2.1 times more delay penalty in the CMOS inverter circuit. This drawback can be addressed using the dual- κ spacers, where high- κ materials are used closer to the gate, while low- κ is near the source/drain junction. Therefore, the value of C GG is lowered by nearly 29%, in comparison with high- k single spacers, while keeping good electrostatic properties. The dual- κ spacer structures using TiO 2 (D2, D4, D6) show a decrease of about 64% for I OFF , as well as better analog performance. Additionally, circuit-level CMOS inverter simulation results for the dual- κ configuration reveal a higher noise margin and gain with controllable delay in comparison with the single- κ spacer structures.