Password-Based Digital Lock With 3-Attempts Security Using Verilog HDL

The Password-Based Digital Lock with 3-Attempt Security Using Verilog HDL is a digital security system designed to provide controlled access through password authentication. The system is implemented using Verilog Hardware Description Language (HDL) and can be programmed on an FPGA board. The user enters a predefined password using input switches or a keypad. The entered password is compared with the stored password using digital logic. If the password matches, the system grants access by activating an unlock signal. If an incorrect password is entered, the system allows the user to retry up to three times. After three consecutive incorrect attempts, the system automatically locks the access and activates a security alert signal. A reset mechanism can be used to restore the system to its initial state. The design uses finite state machine (FSM) concepts, counters, comparators, and sequential logic. This project demonstrates the practical application of Verilog HDL in developing reliable, efficient, and secure digital access control systems.