Improving robustness and variability tolerance in SRAM-based in-memory computing using body bias

In-memory computing (IMC) architectures are regarded as a promising solution for energy-efficient edge applications. However, their computational accuracy and reliability are limited by reduced signal margins, nonlinear multiply-and-accumulate (MAC) operation, power constraints, and high sensitivity to process and device-level variability. In this work, we propose a body bias (BB)-assisted optimization framework to improve the computational efficiency and robustness of SRAM-based IMC architectures. The impact of BB is first analyzed at the bitcell level, focusing on key stability and performance parameters. The analysis is then extended to different IMC architectures to evaluate the influence of BB on signal margin, MAC operation linearity, power consumption, and the number of parallel row activations, which ultimately determines the throughput of the IMC architecture. The results show that controlled BB can be effectively used as a design knob to enhance signal integrity and improve the accuracy of the MAC output. In addition, a variability analysis is performed to identify appropriate BB conditions that mitigate the impact of process variations and device-level mismatches by compensating threshold voltage fluctuations. The proposed BB-assisted approach does not require any array-level modifications and can be dynamically adapted to enable robust, reliable, and energy-efficient SRAM-based IMC design for edge computing applications. The simulation work is carried out in STMicroelectronics 28 nm Fully Depleted Silicon-On-Insulator PDK. The proposed approach achieves up to ∼9 × improvement in robustness to variability, ∼75% increase in average MAC output level, and ∼4 × enhancement in MAC operation throughput for SRAM-based IMC architectures.