A loop-synchronous-regulation-based SET-hardened boost converter

Single-event transients (SETs) in space radiation environments can propagate through the control loop of DC-DC converters, causing duty-cycle anomalies and output-voltage perturbations, thereby degrading the power-supply stability of spacecraft electronic systems. This paper investigates the SET sensitivity and hardening design of the control loop in a peak current-mode-controlled Boost converter, with particular focus on the error-amplifier output node, which is highly susceptible to SETs. First, a circuit-level simulation model is employed to analyze the SET propagation mechanism in the Boost control loop. The error-amplifier output node is identified as the SET-sensitive node, and the effects of load conditions and particle strike timing on output-voltage perturbations are investigated. Based on these analyses, a loop-synchronous-regulation-based SET hardening method is proposed. During an SET event, the current-loop summing node is synchronously regulated to follow the disturbed voltage-loop node, thereby maintaining the voltage difference at the comparator inputs and the duty-cycle signal nearly unchanged, and effectively suppressing SET propagation through the control loop. Based on a commercial 180 nm process, the proposed hardening circuit is verified by simulation in a Boost converter with typical specifications of V IN = 3.7 V, V OUT = 7.6 V, and I OUT = 100 mA. Under an LET of 100 MeV·cm 2 /mg, the hardening circuit suppresses the output-voltage fluctuation to within 1.78 mV, achieving a mitigation capability of 90.19 %. The proposed method effectively enhances the SET tolerance of the Boost converter and provides a circuit-level design reference for SET mitigation in DC-DC converters.