Atomic-scale origin of anomalous crack relocation at heterophase intermetallic interfaces in high-temperature solder interconnects

Increasing computational density and operating temperatures in modern microelectronics expose solder interconnects to severe thermal excursions, making the thermal-cycling reliability of high-temperature solder joints a critical concern. In this study, we demonstrate that cracking still occurs in such solder joints despite the pronounced stress-buffering capability of the Pb-rich matrix. More importantly, the crack location anomalously relocates to the heterophase intermetallic interface rather than the conventional solder/IMC interfaces commonly observed in lead-free solder systems. Double Cs-corrected STEM combined with first-principles calculations are employed to resolve the atomic-scale origins of this unusual cracking behavior. A two-layered IMC architecture forms at solder/pad interface, consisting of a Layer I Ni 3 Sn phase with trace Au incorporation adjacent to pad and an overlying Layer II composed of (Ni, Au) 3 Sn 2 and (Ni, Au)Sn phases. Within the substitutional configurations, Au occupying Ni1 sites exhibits the lowest relaxed total energy. During thermal cycling, interlayer cracking is first detected after 700 cycles and propagates further after 1000 cycles. Thermal-mechanical mismatch between two IMC layers generates a thermal stress estimated to be approximately 40 MPa, providing a thermomechanical driving force for interlayer cracking. Triple junctions connecting grains from both layers serve as preferred sites for defect accumulation. Y-type triple junction exhibits disconnection activity and pile-up, leading to strain concentration and mobility depletion, whereas T-type triple junction undergoes stagnation accompanied by lattice distortion, atomic shuffling and disordering, offering structurally weakened pathways for interlayer cracking.