Physical Origin and Mitigation of Output-Capacitance Hysteresis in Superjunction Devices

The output-capacitance hysteresis of charge-balanced vertical drift regions, commonly referred to as superjunctions, has attracted renewed attention because of its impact on switching losses in resonant and soft-switching power converters. Previous studies have linked this behaviour to stranded charge in the p/n semiconductor pillars and to the finite carrier velocity required for charge redistribution during voltage transients. In this work, the physical origin of this hysteresis is revisited by analysing the charge dynamics during charging and discharging. Finite-element simulations are used to assess the influence of charge-balance condition, temperature, partial dopant ionisation, cell pitch, voltage slew rate, and non-uniform doping, including graded pillar profiles. The results indicate that capacitance hysteresis is strongly governed by field-dependent carrier transport at the boundaries of the depletion regions, which controls the rate at which mobile carriers can be removed from, or replenished within, the charge-balanced structure. Based on these findings, design guidelines are proposed that reduce hysteresis-related energy loss by approximately 30% compared with a uniformly doped reference superjunction structure, while preserving a favourable specific on-state resistance, Ron,sp, and without substantially increasing process complexity.