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This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1. 2 V down to 0. 26 V with the read access time from 6 ns to 0. 85 s. Minimum energy of 2. 07 pJ is achieved at 0. 4 V with 40. 3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29. 4% between 0. 38 V 0. 6 V by the proposed CAM-assisted circuit.
Wang et al. (Mon,) studied this question.