What question did this study set out to answer?

The aim is to develop efficient test access architectures for core-based system-on-chip designs under specific constraints.

January 1, 2000Open Access

Design of system-on-a-chip test access architectures under place-and-route and power constraints

KCKrishnendu ChakrabartyTechno India Group (India)

Key Points

The aim is to develop efficient test access architectures for core-based system-on-chip designs under specific constraints.
Utilized integer linear programming (ILP) to create access architectures.
Incorporated place-and-route and power consumption constraints in the models.
Applied case studies on two representative system-on-chip designs using public-domain ILP software.
Proposed architectures effectively address test access challenges in SOCs.
Models demonstrate significant improvements in system-level power management.
ILP solutions confirm the feasibility of testing embedded cores within stated constraints.

Abstract

Test access is a difficult problem encountered in the testing of core-based system-on-a-chip (SOC) designs. Since embedded cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms are required to test them at the system level. We propose test access architectures based on integer linear programming (ILP) that incorporate place-and-route constraints arising from the functional interconnections between cores, as well as system-level constraints on power consumption. As a case study, we apply the ILP models to two representative SOCs, and solve them using a public-domain ILP software package.

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