A phase-locked loop clock generator for a 1 GHz microprocessor

The design of a fully-integrated phase-locked loop (PLL) clock generator for a 1.0 GHz microprocessor using a 1.8 V, 0.25 /spl mu/m digital CMOS6X process is described. Hardware measurements are included, showing low jitter (</spl plusmn/36 ps active processor, </spl plusmn/9 ps quiet), high maximum lock frequency (1560 MHz), and wide lock range (1.9:1).