Hardware-based FIR filter implementations for ECG signal denoising: A monitoring framework from industrial electronics perspective

This work represents the design and verification of three different finite impulse response (FIR) filter implementations for removing the noise of electrocardiogram (ECG) signals. Generally, ECG signals may be contaminated with different noise sources such as body movement and respiration, electromyography (EMG) interference, power line interference and the baseline wander noise. The FIR filter coefficients are calculated to attenuate the 60 Hz frequencies. The advanced filter design tool available with MATLAB is used to first determine the FIR filter coefficients. These coefficients are then used in three different FIR filter implementations: regular implementation, pipelined implementation and pipelined multiply-accumulate (MAC) implementation. The three implementations are designed using VHDL and the Quartus II design toolset. A test bench is also designed to verify the operation of each filter implementation, and the Modelsim simulator available with Quartus is used to run the tests. The synthesized reports for the three different implementations show the resource utilization and the maximum operating frequency. As a result, the regular (direct) design produces the simplest design but consumes more resources and operates at lower frequencies. The pipelined architecture consumes more resources but it enhances the operating frequency. The pipelined MAC implementation requires the least resources and operates at extremely higher performance, however, the main drawback is its complexity. The hardware implementations can be further viewed as an industrial ECG monitoring framework where system dynamics modeling can be applied to minimize the risks associated with the framework using any of the three implementations.