The Design of 3D‐Interface Architecture in an Ultralow‐Power, Electrospun Single‐Fiber Synaptic Transistor for Neuromorphic Computing

Synaptic electronics is a new technology for developing functional electronic devices that can mimic the structure and functions of biological counterparts. It has broad application prospects in wearable computing chips, human-machine interfaces, and neuron prostheses. These types of applications require synaptic devices with ultralow energy consumption as the effective energy supply for wearable electronics, which is still very difficult. Here, artificial synapse emulation is demonstrated by solid-ion gated organic field-effect transistors (OFETs) with a 3D-interface conducting channel for ultralow-power synaptic simulation. The basic features of the artificial synapse, excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and high-pass filtering, are successfully realized. Furthermore, the single-fiber based artificial synapse can be operated by an ultralow presynaptic spike down to -0.5 mV with an ultralow reading voltage at -0.1 mV due to the large contact surface between the ionic electrolyte and fiber-like semiconducting channel. Therefore, the ultralow energy consumption at one spike of the artificial synapse can be realized as low as ≈3.9 fJ, which provides great potential in a low-power integrated synaptic circuit.