Sources of variability in scaled MoS2 FETs

Through advances in growth, cleaning, and device fabrication, our scaled MoS 2 FET flow has reached sufficient maturity to study variability. We show devices with median SS min 80mV/dec and I max >100µA/µm and find that thinning down the MoS 2 channel from three to one layer results in strongly reduced SS and V T variability, despite the presence of second layer MoS 2 crystals. The scaling of σV T with device dimensions of the thin-channel MoS 2 FETs with EOT=2.6nm is found nearly on par with state-of-the-art Si finFETs at EOT=0.8nm, with a Pelgrom slope of A Vt =2.8mV.µm. Finally, by directly correlating physical characterization, electrical measurements and 3D TCAD simulations, we identify second layer islands as a significant contributor to SS degradation and variability.