December 23, 2002

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

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Abstract

A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Key Points

Abstract

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