A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

T. Saeki; Y. Nakaoka; M. Fujita; A. Tanaka; K. Nagata; Keiichiro SAKAKIBARA; T. Matano; Yuuji HOSHINO; K. Miyano; S. Isa; E. Kakehashi; J.M. Drynan; M. Komuro; T. Fukase; H. Iwasaki; J. Sekine; M. Igeta; N. Nakanishi; T. Itani; Kodai YOSHIDA; H. Yoshino; S. Hashimoto; T. Yoshii; M. Ichinose; T. Imura; M. Uziie; K. Koyama; Y. Fukuzo; T. Okuda

doi:10.1109/isscc.1996.488723

Ask about this paper

Answers are grounded in this paper and cite their sources.

Abstract

A 245.7 mm/sup 2/ 256 Mb SDRAM uses: (1) 60.2% cell-occupancy ratio array, (2) prefetched pipeline using first-in first-out buffer with parallel/serial converter, (3) synchronous mirror delay circuit.

Discussion

No takes yet. Share an insight, caveat, or question.

Cite This Study

Saeki et al. (2002) studied this question.

synapsesocial.com/papers/6a21496957668066d6c3df7c https://doi.org/10.1109/isscc.1996.488723

View at Publisher

Ask AI

Bookmark

Share

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Ask about this paper

Abstract

Discussion

Cite This Study

A 2.5 ns clock access 250 MHz 256 Mb SDRAM with a synchronous mirror delay

Ask about this paper

Abstract

Discussion

Cite This Study

Keep reading

Keep reading