GAA Technology Innovations for 2nm Logic node and Beyond

We consider GAA transistor performance, SRAM cell design, and MOL/BEOL interconnect resistance reduction at N2 node dimensions. We demonstrate schemes to reduce the N2 GAA resistance components to improve the transistor drive current and evaluate circuit performance using our MSCO™ simulation platform. SRAM MSCO™ simulations are used to evaluate optimization strategies for N2 GAA SRAM and show improved stability, writability and read-write current. We present MOL and BEOL innovations, critical to interconnect resistance reduction, and show the circuit-level performance benefits from MSCO™ simulations.