Design Technology Co-Optimization for Gate-All-Around Nanosheet Transistors Considering Source/Drain Confinement and Post-Gate Single Diffusion Break

In this work, a novel self-aligned source/drain confinement (SA-SDC) scheme is proposed to enable the downsizing of gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs). Compared with the traditional diamond-shaped source/drain (S/D) epitaxy, the proposed SA-SDC scheme suppresses the lateral over expansion and facilitates wrap-around contact (WAC) formation, resulting in the decrease of device area, parasitic capacitance (C₏₀ₑ₀), and resistance (R₏₀ₑ₀). A calibrated 3-D TCAD simulation demonstrates a 35% reduction in the device RC delay for the SA-SDC NS FET. Considering various device structures and channel stress variations induced by diffusion break integration schemes, a comprehensive investigation of the 15-stage ring oscillator (RO) is conducted. By integrating the stress-enhanced postgate single diffusion break (PG-SDB) process, the SA-SDC NAND2 cell achieves an additional 21% reduction in the power dissipation or a 9% increase in the frequency. Power, performance, and area (PPA) are also collaboratively optimized for different applications using the quantitative quality factor. Particularly, the NAND2 cell is optimized within the constrained footprint. The cell, with 30–40-nm NS width of the n-type device, exhibits the optimal and robust performance for all the simulated technology/design options.