Key points are not available for this paper at this time.
This paper provides a unique reduced component-count-efficient topology for 125-level asymmetrical multilevel inverter. The proposed design uses asymmetric DC sources and an H-bridge to produce an output voltage that can reach a maximum of 125 levels. The design and development of a multi-level inverter with a stacked half-bridge architecture that generates a 125-level output with excellent power quality is the object of the current research. The MOSFETs are triggered using a fundamental frequency switching technique that has been modified for output voltage level control. At its output, the level production circuit exclusively generates positive levels. Look-up tables are employed to regulate MOSFETs, and an H-bridge circuit is used to create polarities. 125 levels of output result in a nearly sinusoidal voltage waveform, which will give a nearly sinusoidal voltage waveform without the use of filters. The proposed work is Simulated in MATLAB/Simulink software.
Kumar et al. (Sat,) studied this question.