What question did this study set out to answer?

This research aims to implement a neural network filtering algorithm to reduce noise from ray-tracing, utilizing hardware accelerators.

April 29, 2026Open Access

Implementation of Deep Learning based Rendering De-Noising Accelerator

Key Points

This research aims to implement a neural network filtering algorithm to reduce noise from ray-tracing, utilizing hardware accelerators.
Implemented a neural network with multiple layers and five processing stages: IDLE, SIGN, MUL, SUM, and ACT.
Each stage processes one cycle via a finite state machine, using fixed point operations.
Synthesized the implemented design in Verilog HDL for FPGA operation up to 185MHz.
Successfully achieved rapid filtering with 10 neurons in a hidden layer handling 36 inputs and 6 output neurons managing 10 inputs each.
The processing sequence consists of 10 cycles to extract filtering parameters while maintaining fast computation speeds.

Abstract

Background/Objectives: In this paper, we implemented the neural network of learning based filtering algorithm, which eliminates noise generated by ray-tracing, through Verilog HDL. Methods/Statistical analysis: The neurons used in the learning based filtering algorithm are divided into five stages: IDLE, SIGN, MUL, SUM, and ACT. Each stage is processed in one cycle through the FSM(Finite State Machine).These neurons were organized into a number of layers. The operation used fixed point. Findings: The neural network has a large amount of computation, but since the computation is simple, it can be processed quickly by hardware implementation. It has a hidden layer (10 neurons with 36 inputs), an output layer (6 neurons with 10 inputs), each layer has 5 stages, so you can get the filtering parameters after 10 cycles. Improvements/Applications: Verilog HDL can be synthesized and downloaded to the FPGA to operate up to 185MHz.

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