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This research explores methods to achieve stable threshold voltage and high mobility in dual-gate a-IGZO transistors.

August 1, 2026Advanced Functional Materials0 citationsOpen Access

Simultaneous Enhancement of Performance and Stability in Dual‐Gate a‐IGZO Thin‐Film Transistors via Single‐Step Laser Annealing for Capacitor‐Less DRAM

Key Points

This research explores methods to achieve stable threshold voltage and high mobility in dual-gate a-IGZO transistors.
Introduced spatially selective laser annealing in single-step process.
Measured characteristics of dual-gate a-IGZO TFTs including threshold voltage, field-effect mobility, and contact resistance.
Evaluated device stability under bias stress over extended operation time.
Achieved field-effect mobility of 37.9 cm² V⁻¹ s⁻¹ and stable threshold voltage of 0.27 V.
Demonstrated stable operation with small ΔV th under bias stress for over 10,000 s.
Maintained reliable '0/1' state discrimination with memory windows exceeding 10⁵.

Abstract

ABSTRACT Wide‐bandgap amorphous oxide semiconductors (AOSs), particularly indium‐gallium‐zinc‐oxide (IGZO), offer ultralow off‐current and back‐end‐of‐line compatibility, making them attractive for advanced dynamic random access memory (DRAM). In capacitor‐less two‐transistor (2T0C) DRAM, dual‐gate (DG) a‐IGZO TFTs are promising read transistors, but achieving a stable positive threshold voltage (V th ) typically reduces field‐effect mobility (µ FE ) and increases contact resistance (R C ), limiting fast operation. This study introduces a spatially selective laser annealing strategy that overcomes this limitation in a single step. The steep thermal gradient promotes oxygen incorporation at the top‐gate dielectric/channel interface, passivating defects without severely depleting carrier density. Simultaneously, WO x interlayer removal combined with oxygen redistribution forms conductive n + regions at source/drain contacts. This dual modification stabilizes the channel and reduces R C , enabling both high µ FE (37.9 cm 2 V −1 s −1 ) and a stable positive V th (0.27 V). The optimized devices exhibit small ΔV th under bias stress and reliable operation, demonstrating the read function of 2T0C DRAM, maintaining stable “0/1” state discrimination and wide memory windows (>10 5 ) for over 10 000 s. This single‐step process provides a practical route to overcome the performance‐stability trade‐off in AOS TFTs, highlighting strong potential for emerging memory applications.

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