Jitter Injection Techniques in High Speed SerDes Test

ABSTRACT With the widespread implementation of smart grids, the communication bandwidth of such systems continues to grow. As a result, jitter injection has become a common practice in system reliability test to evaluate timing robustness under realistic operating conditions. In the past research, only random jitter injection was implemented through phase interpolation techniques. To thoroughly investigate the impact of jitter on signal transmission, this study introduces an innovative jitter injection scheme based on phase adjustment and jitter decomposition principles. Specifically, this paper utilised a direct digital synthesis (DDS)‐based jitter synthesis technique and a jitter transmission model in phase‐locked loop (PLL) to realise a more complex jitter injection. This integration enables accurate injection of different jitter components in the amplitude spectrum from 0 to 2UI in high‐speed SerDes systems. To validate the effectiveness of the proposed scheme, a high‐speed serial link test platform was developed, which utilises the novel jitter injection method to characterise critical signal metrics, such as eye diagrams and distribution histogram. Experimental results demonstrate that the proposed scheme effectively replicates both random and periodic jitter present in communication links, thereby providing robust technical support for the design and optimisation of high‐speed serial link systems.