This study describes the design, simulation, and comparative analysis of 5-stage and 7-stage CMOS ring oscillator circuits in 45 nm and 180 nm technology nodes, a combination not previously reported in the open literature under similar conditions. This study quantifies the improvements in oscillatory frequency, power dissipation, propagation time, phase noise, and jitter as the scaling of the transistor progresses at nominal supply voltages of 1.2 V and 1.8 V, respectively. The simulation results obtained using the Cadence Virtuoso environment have been validated using a more accurate analytical model implemented in the Python environment, achieving an average accuracy above 90%. Using a 3000-point dataset, a Gradient Boosting-based machine learning algorithm has been trained to achieve R2 score 0.9973 and MAPE 1.16%. Using a Particle Swarm Optimization algorithm, a reduction in power dissipation is achieved by 11.9% along with a reduction in simulation runs using the Cadence environment by 66.7%.Comparative analysis with the results reported in the recent literature on the design and analysis of ring oscillator circuits published in the years 2019–2025 reveals the competitive nature of the proposed 7-stage 45 nm ring oscillator design, where the normalized jitter is 1.670%, which is superior to the 5-stage design and is accompanied by a phase noise of -98.6dBc/Hz at a 1 MHz offset.
Shiva et al. (Sat,) studied this question.
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