Timing closure in integrated circuit physical design requires coordinating fixes across multiple analysis domains—setup/hold timing, design rule checking (DRC), and physical optimization—that are traditionally handled by separate EDA tools with no shared context. A timing fix that resolves a setup violation may introduce new violations when the increased cell capacitance degrades neighboring paths, requiring multiple manual iterations that consume 40–60% of the back-end design schedule. We present a multi-agent architecture in which three specialized Large Language Model (LLM) agents—TimingAgent, DRCAgent, and PhysicalAgent—are composed into a sequential state-machine graph using LangGraph, where each downstream agent receives the structured output of its upstream predecessors as context. The key architectural contribution is cross-stage context propagation: the Physical Agent receives both timing violation data and DRC congestion state before generating Engineering Change Order (ECO) commands, enabling it to select conservative cell-sizing strategies that limit capacitance increase on shared nets. We evaluate the architecture on three OpenROAD benchmark designs—GCD (~223 cells), AES cipher (~20K cells), and ibex RISC-V core (~15K cells) —using the SkyWater 130nm PDK. For each design, we compare a baseline (no ECO), single-agent aggressive upsizing, and multi-agent conservative upsizing, all measured via replacecell → incremental global route → parasitic estimation → STA on the fully routed design. The multi-agent approach improved or matched WNS on all three designs (never worse), while single-agent aggressive upsizing worsened WNS on two of three. On the ibex RISC-V core, multi-agent improved WNS by +18. 8 ps while single-agent aggressive upsizing worsened it by −13. 0 ps—a 31. 8 ps gap that grows with critical-path length.
Gursimran S Sodhi (Tue,) studied this question.