A FPGA‐Based Modular Multiplication With New Hybrid DSP‐LUT Method

ABSTRACT Modular multiplication (MM) includes multiplication and modular reduction operations. In FPGA platform, DSP blocks provide the most efficient multipliers, and they should be used whenever possible. In this paper, we propose an area‐efficient DSP‐based pipeline MM on FPGA platform, which explores various optimization methods for multiplier and modular reduction. Firstly, we review the multiplier design of the previous pipeline MM, and analyze their potential issues in DSP utilization. Secondly, we propose a new three‐step ‐term hybrid DSP‐LUT Karatsuba scalar multiplication (KSM) to solve the problem of insufficient DSP utilization caused by the misalignment of bit‐width between the required multiplier and the multiplier of DSP block. Finally, an optimized hybrid‐memory method and the ternary adder–based compressor are proposed to reduce the cost of modular reduction. The proposed pipeline MM is implemented on the Xilinx Virtex‐7 platform. Compared with the previous state‐of‐the‐art pipeline DSP‐based designs, the equivalent number of slice (ENS) metrics of the proposed MM are only 29.6%/21.4%/26.1%/23.6% of them when word size .