This study evaluates the improvement in the trade-off between switching loss and ringing provided by gate-drive level optimization for both the turn-on and turn-off operations of superjunction metal-oxide semiconductor field-effect transistors (MOSFETs). A gate-drive circuit integrating a field programmable gate array (FPGA) and a driver integrated circuit (IC) was prototyped, enabling dynamic switching of the gate-drive level to a lower value for a short duration to reduce switching speed, based on feedback signals to the analog-to-digital converter (ADC) terminal. A lookup table (LUT) was constructed to determine the drain current and timing for gate-level adjustment under various load conditions. Inductive load switching was simulated using a device model developed with BSIM3 and voltage-dependent capacitors, and the optimal timing for gate-level transition was analyzed. Experimental results demonstrated effective suppression of switching surge and ringing compared with conventional constant-level gate drive, with minimal degradation in switching loss.
Yasuzumi et al. (Sun,) studied this question.