PulseExploreJournal ClubDebatesTrendingResearchersJournals
Instagram
HomeExploreJournal ClubTrending
Synapse
⌘+K
Synapse
October 1, 201611 citations

Hardware-based FIR filter implementations for ECG signal denoising: A monitoring framework from industrial electronics perspective

View Full Paper
SASalam Al-KhammasiKAKhald A. I. AboalayonMDMohammad Daneshzand

Key Result

The pipelined MAC implementation of FIR filters for ECG denoising required the least resources and operated at the highest performance compared to regular and pipelined architectures.

Structured PICO

P
Population
ECG signals
I
Intervention
Three different finite impulse response (FIR) filter implementations (regular, pipelined, and pipelined multiply-accumulate [MAC]) designed using VHDL and Quartus II
C
Comparator
Comparison among the three filter implementations
O
Outcome
Resource utilization and maximum operating frequency

A pipelined MAC implementation of FIR filters for ECG denoising offers the best balance of low resource utilization and high operating frequency, despite increased design complexity.

Limitations

  • Complexity of the pipelined MAC implementation

Abstract

This work represents the design and verification of three different finite impulse response (FIR) filter implementations for removing the noise of electrocardiogram (ECG) signals. Generally, ECG signals may be contaminated with different noise sources such as body movement and respiration, electromyography (EMG) interference, power line interference and the baseline wander noise. The FIR filter coefficients are calculated to attenuate the 60 Hz frequencies. The advanced filter design tool available with MATLAB is used to first determine the FIR filter coefficients. These coefficients are then used in three different FIR filter implementations: regular implementation, pipelined implementation and pipelined multiply-accumulate (MAC) implementation. The three implementations are designed using VHDL and the Quartus II design toolset. A test bench is also designed to verify the operation of each filter implementation, and the Modelsim simulator available with Quartus is used to run the tests. The synthesized reports for the three different implementations show the resource utilization and the maximum operating frequency. As a result, the regular (direct) design produces the simplest design but consumes more resources and operates at lower frequencies. The pipelined architecture consumes more resources but it enhances the operating frequency. The pipelined MAC implementation requires the least resources and operates at extremely higher performance, however, the main drawback is its complexity. The hardware implementations can be further viewed as an industrial ECG monitoring framework where system dynamics modeling can be applied to minimize the risks associated with the framework using any of the three implementations.

Ask AI
Helpful
Bookmark
Share
View Full Paper

Cite This Study

Al-Khammasi et al. (2016) studied ECG signal noise. FIR filter implementations (regular, pipelined, pipelined MAC) was evaluated on Resource utilization and maximum operating frequency. The pipelined MAC implementation of FIR filters for ECG denoising required the least resources and operated at the highest performance compared to regular and pipelined architectures.

synapsesocial.com/papers/6a1ff4983f3a87967f2e5fc6https://doi.org/10.1109/ct-ieta.2016.7868243
Ask AI
Helpful
Bookmark
Share
View Full Paper