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We study the impact of different interlayers (ILs) and ferroelectric materials on charge trapping during the endurance fatigue of Si ferroelectric field effect transistor (FeFET) with TiN/HfxZr1-xO2/ interlayer/Si (MFIS) gate-stack. We have fabricated FeFET devices with different interlayers (SiO2 or SiON) and HfxZr1-xO2 materials (x =0. 75, 0. 6, 0. 5) and directly extracted the charge trapping during endurance fatigue. We find that: 1) under the same equivalent oxide thickness (EOT) condition, the increase of dielectric constant and interlayer thickness suppresses charge trapping and improves the endurance characteristics; 2) charge trapping effect is experimentally verified to be the origin of endurance fatigue; and 3) as the spontaneous polarization (P ₒ) of the HfxZr1-xO2 decreases from 25. 9~ C /cm2 (Hf0. 5Zr0. 5O2) to 20. 3~ C /cm2 (Hf0. 6Zr0. 4O2), the charge trapping behavior decreases, resulting in the slow degradation rate of memory window (MW) during program/erase cycling; in addition, when P ₒ further decreases to 8. 1~ C /cm2 (Hf0. 75Zr0. 25O2), the initial MW nearly disappears (only ~0. 02 V). Thus, the reduction of P ₒ could improve endurance characteristics. On the contrary, it can also reduce the MW. Our work helps design the MFIS gate-stack to improve endurance characteristics.
Tian et al. (Wed,) studied this question.